// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_dma_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_DMA_REG_REG_OFFSET_H__
#define __HIPCIEC_AP_DMA_REG_REG_OFFSET_H__

/* HIPCIEC_AP_DMA_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE                       (0)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_AP_DMA_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x0)    /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x100)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x200)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x300)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_4_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x400)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_5_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x500)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_6_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x600)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_7_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x700)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_8_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x800)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_9_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x900)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_10_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA00)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_11_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB00)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_12_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC00)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_13_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD00)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_14_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE00)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_15_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF00)  /* DMA Queue SQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x4)    /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x104)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x204)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x304)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_4_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x404)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_5_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x504)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_6_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x604)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_7_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x704)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_8_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x804)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_9_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x904)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_10_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA04)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_11_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB04)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_12_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC04)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_13_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD04)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_14_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE04)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_15_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF04)  /* DMA Queue SQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x8)    /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x108)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x208)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_3_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x308)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_4_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x408)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_5_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x508)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_6_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x608)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_7_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x708)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_8_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x808)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_9_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x908)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_10_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA08)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_11_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB08)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_12_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC08)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_13_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD08)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_14_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE08)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_15_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF08)  /* DMA Queue SQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC)    /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x10C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_3_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x30C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_4_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x40C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_5_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x50C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_6_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x60C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_7_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x70C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_8_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x80C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_9_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x90C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_10_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA0C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_11_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB0C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_12_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC0C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_13_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD0C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_14_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE0C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_15_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF0C)  /* DMA Queue SQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x10)   /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x110)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x210)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x310)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_4_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x410)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_5_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x510)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_6_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x610)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_7_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x710)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_8_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x810)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_9_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x910)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_10_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA10)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_11_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB10)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_12_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC10)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_13_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD10)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_14_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE10)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_15_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF10)  /* DMA Queue CQ Base Address Low Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x14)   /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x114)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x214)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x314)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_4_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x414)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_5_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x514)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_6_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x614)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_7_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x714)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_8_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x814)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_9_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x914)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_10_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA14)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_11_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB14)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_12_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC14)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_13_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD14)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_14_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE14)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_15_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF14)  /* DMA Queue CQ Base Address High Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x18)   /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x118)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x218)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_3_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x318)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_4_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x418)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_5_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x518)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_6_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x618)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_7_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x718)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_8_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x818)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_9_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x918)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_10_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA18)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_11_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB18)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_12_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC18)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_13_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD18)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_14_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE18)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_15_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF18)  /* DMA Queue CQ Depth */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x1C)   /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x11C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x21C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_3_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x31C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_4_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x41C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_5_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x51C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_6_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x61C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_7_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x71C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_8_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x81C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_9_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x91C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_10_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA1C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_11_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB1C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_12_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC1C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_13_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD1C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_14_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE1C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_15_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF1C)  /* DMA Queue CQ Head Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20)   /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x120)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x220)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x320)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x420)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x520)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x620)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x720)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x820)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x920)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA20)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB20)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC20)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD20)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE20)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL0_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF20)  /* DMA Queue control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x24)   /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x124)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x224)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x324)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x424)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x524)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x624)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x724)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x824)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x924)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA24)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB24)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC24)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD24)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE24)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL1_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF24)  /* DMA Queue control Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_0_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x28)   /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_1_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x128)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_2_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x228)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_3_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x328)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_4_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x428)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_5_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x528)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_6_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x628)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_7_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x728)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_8_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x828)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_9_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x928)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_10_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA28)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_11_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB28)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_12_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC28)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_13_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD28)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_14_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE28)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_15_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF28)  /* DMA Queue Reserved Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x30)   /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x130)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x230)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_3_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x330)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_4_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x430)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_5_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x530)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_6_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x630)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_7_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x730)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_8_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x830)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_9_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x930)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_10_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA30)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_11_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB30)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_12_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC30)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_13_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD30)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_14_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE30)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_FSM_STS_15_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF30)  /* DMA Queue FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x34)   /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x134)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x234)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x334)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x434)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x534)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x634)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x734)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x834)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x934)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA34)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB34)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC34)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD34)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE34)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_STS_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF34)  /* DMA Queue SQ and CQ status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x38)   /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x138)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x238)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_3_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x338)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_4_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x438)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_5_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x538)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_6_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x638)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_7_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x738)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_8_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x838)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_9_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x938)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_10_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA38)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_11_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB38)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_12_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC38)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_13_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD38)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_14_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE38)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_15_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF38)  /* Byte counter for current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x3C)   /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x13C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x23C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_3_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x33C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_4_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x43C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_5_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x53C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_6_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x63C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_7_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x73C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_8_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x83C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_9_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x93C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_10_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA3C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_11_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB3C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_12_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC3C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_13_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD3C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_14_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE3C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_15_REG     (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF3C)  /* DMA Queue CQ Tail Pointer Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x40)   /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x140)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x240)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_3_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x340)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_4_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x440)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_5_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x540)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_6_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x640)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_7_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x740)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_8_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x840)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_9_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x940)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_10_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA40)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_11_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB40)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_12_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC40)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_13_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD40)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_14_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE40)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_STS_15_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF40)  /* DMA Queue Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x44)   /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x144)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x244)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_3_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x344)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_4_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x444)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_5_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x544)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_6_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x644)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_7_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x744)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_8_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x844)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_9_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x944)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_10_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA44)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_11_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB44)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_12_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC44)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_13_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD44)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_14_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE44)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MSK_15_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF44)  /* DMA Queue Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x50)   /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x150)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x250)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x350)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x450)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x550)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x650)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x750)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x850)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x950)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA50)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB50)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC50)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD50)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE50)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP0_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF50)  /* The 1st DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x54)   /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x154)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x254)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x354)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x454)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x554)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x654)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x754)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x854)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x954)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA54)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB54)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC54)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD54)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE54)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP1_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF54)  /* The 2nd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x58)   /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x158)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x258)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x358)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x458)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x558)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x658)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x758)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x858)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x958)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA58)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB58)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC58)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD58)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE58)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP2_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF58)  /* The 3rd DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x5C)   /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x15C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x25C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x35C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x45C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x55C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x65C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x75C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x85C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x95C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA5C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB5C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC5C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD5C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE5C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP3_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF5C)  /* The 4th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x60)   /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x160)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x260)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x360)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_4_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x460)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_5_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x560)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_6_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x660)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_7_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x760)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_8_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x860)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_9_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x960)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_10_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA60)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_11_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB60)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_12_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC60)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_13_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD60)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_14_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE60)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_15_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF60)  /* The address[31:0] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x64)   /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x164)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x264)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x364)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_4_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x464)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_5_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x564)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_6_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x664)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_7_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x764)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_8_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x864)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_9_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x964)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_10_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA64)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_11_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB64)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_12_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC64)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_13_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD64)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_14_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE64)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_15_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF64)  /* The address[63:32] of error. */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_0_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x68)   /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_1_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x168)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_2_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x268)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_3_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x368)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_4_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x468)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_5_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x568)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_6_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x668)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_7_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x768)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_8_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x868)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_9_REG  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x968)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_10_REG (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA68)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_11_REG (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB68)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_12_REG (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC68)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_13_REG (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD68)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_14_REG (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE68)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_READ_ERR_PTR_15_REG (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF68)  /* The ptr address of SQ read err */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x6C)   /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x16C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x26C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x36C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x46C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x56C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x66C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x76C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x86C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x96C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA6C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB6C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC6C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD6C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE6C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_RO_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF6C)  /* DMA Queue Interrupt RO Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x70)   /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x170)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x270)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_3_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x370)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_4_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x470)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_5_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x570)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_6_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x670)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_7_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x770)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_8_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x870)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_9_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x970)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_10_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA70)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_11_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB70)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_12_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC70)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_13_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD70)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_14_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE70)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_SET_15_REG         (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF70)  /* DMA Queue Interrupt SET Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x74)   /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x174)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x274)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x374)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x474)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x574)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x674)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x774)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x874)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x974)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA74)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB74)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC74)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD74)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE74)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP4_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF74)  /* The 5th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x78)   /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x178)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x278)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x378)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x478)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x578)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x678)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x778)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x878)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x978)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA78)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB78)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC78)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD78)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE78)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP5_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF78)  /* The 6th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x7C)   /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x17C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x27C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x37C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x47C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x57C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x67C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x77C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x87C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x97C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA7C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB7C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC7C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD7C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE7C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP6_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF7C)  /* The 7th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x80)   /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x180)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x280)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x380)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x480)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x580)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x680)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x780)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x880)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x980)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA80)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB80)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC80)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD80)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE80)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_DESP7_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF80)  /* The 8th DW of current descriptor */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x84)   /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x184)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x284)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x384)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x484)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x584)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x684)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x784)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x884)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x984)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA84)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB84)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC84)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD84)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE84)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM0_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF84)  /* The statistics number for dma_queu_err0/1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x88)   /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x188)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x288)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x388)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x488)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x588)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x688)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x788)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x888)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x988)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA88)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB88)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC88)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD88)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE88)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM1_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF88)  /* The statistics number for dma_queu_err2/3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x8C)   /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x18C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x28C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x38C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x48C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x58C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x68C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x78C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x88C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x98C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA8C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB8C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC8C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD8C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE8C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM2_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF8C)  /* The statistics number for dma_queu_err4/5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x90)   /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x190)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x290)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x390)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x490)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x590)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x690)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x790)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x890)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x990)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA90)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB90)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC90)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD90)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE90)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM3_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF90)  /* The statistics number for dma_queu_err6/7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x94)   /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x194)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x294)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x394)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x494)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x594)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x694)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x794)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x894)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x994)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA94)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB94)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC94)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD94)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE94)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM4_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF94)  /* The statistics number for dma_queu_err8/9 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x98)   /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x198)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x298)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x398)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x498)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x598)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x698)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x798)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x898)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x998)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA98)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB98)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC98)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD98)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE98)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ERR_INT_NUM5_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF98)  /* The statistics number for dma_queu_err10/11 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x9C)   /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x19C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x29C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x39C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x49C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x59C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x69C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x79C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_8_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x89C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_9_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x99C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_10_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA9C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_11_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xB9C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_12_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xC9C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_13_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xD9C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_14_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xE9C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_QUEUE_CTRL2_15_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xF9C)  /* DMA Queue control Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_0_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xA0)   /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_1_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x1A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_2_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_3_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x3A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_4_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x4A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_5_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x5A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_6_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x6A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_7_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x7A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_8_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x8A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_9_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x9A0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_10_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xAA0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_11_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xBA0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_12_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xCA0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_13_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xDA0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_14_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xEA0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DONE_INT_MERGE_15_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0xFA0)  /* DONE interrupt merge ctrl register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ECC_RESERVED_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2000) /* ECC inject register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ECC_ERR_ADDR_REG             (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2004) /* ECC err address register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_ECC_ECC_CNT_REG              (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2014) /* ECC err cnt register */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_EP_INT_MSK_REG               (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2024) /* DMA_EP_INT_MSK */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_EP_INT_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2028) /* DMA_EP_INT */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_DMA_EP_INT_STS_REG               (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x202C) /* DMA_EP_INT_STS */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_COMMON_AND_CH0_ERR_STS_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2030) /* COMMON_AND_CH0_ERR_STS */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_ATOMIC_CTRL_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2038) /* ATOMIC_CTRL */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x203C) /* EP0_ATOMIC_HEADER_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2040) /* EP0_ATOMIC_HEADER_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2044) /* EP0_ATOMIC_HEADER_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_3_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2048) /* EP0_ATOMIC_HEADER_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x204C) /* EP0_ATOMIC_DATA_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2050) /* EP0_ATOMIC_DATA_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2054) /* EP0_ATOMIC_DATA_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2058) /* EP0_ATOMIC_DATA_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x205C) /* EP0_ATOMIC_DATA_4 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2060) /* EP0_ATOMIC_DATA_5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2064) /* EP0_ATOMIC_DATA_6 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2068) /* EP0_ATOMIC_DATA_7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x206C) /* EP0_ATOMIC_RESP_DATA_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2070) /* EP0_ATOMIC_RESP_DATA_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2074) /* EP0_ATOMIC_RESP_DATA_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2078) /* EP0_ATOMIC_RESP_DATA_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_4_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x207C) /* EP0_ATOMIC_RESP_DATA_4 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_5_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2080) /* EP0_ATOMIC_RESP_DATA_5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_6_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2084) /* EP0_ATOMIC_RESP_DATA_6 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_7_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2088) /* EP0_ATOMIC_RESP_DATA_7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x208C) /* EP1_ATOMIC_HEADER_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2090) /* EP1_ATOMIC_HEADER_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2094) /* EP1_ATOMIC_HEADER_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_3_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2098) /* EP1_ATOMIC_HEADER_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x209C) /* EP1_ATOMIC_DATA_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20A0) /* EP1_ATOMIC_DATA_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20A4) /* EP1_ATOMIC_DATA_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20A8) /* EP1_ATOMIC_DATA_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20AC) /* EP1_ATOMIC_DATA_4 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20B0) /* EP1_ATOMIC_DATA_5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_6_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20B4) /* EP1_ATOMIC_DATA_6 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_7_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20B8) /* EP1_ATOMIC_DATA_7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20BC) /* EP1_ATOMIC_RESP_DATA_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20C0) /* EP1_ATOMIC_RESP_DATA_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20C4) /* EP1_ATOMIC_RESP_DATA_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20C8) /* EP1_ATOMIC_RESP_DATA_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_4_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20CC) /* EP1_ATOMIC_RESP_DATA_4 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_5_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20D0) /* EP1_ATOMIC_RESP_DATA_5 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_6_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20D4) /* EP1_ATOMIC_RESP_DATA_6 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_7_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20D8) /* EP1_ATOMIC_RESP_DATA_7 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_ATOMIC_RESP_DATA_ST_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20DC) /* ATOMIC_RESP_DATA_ST */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_ID_STS_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20E0) /* EP0_LOCAL_CPL_ID_STS_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_ID_STS_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20E4) /* EP0_LOCAL_CPL_ID_STS_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_ID_STS_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20E8) /* EP0_LOCAL_CPL_ID_STS_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_ID_STS_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20EC) /* EP0_LOCAL_CPL_ID_STS_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_ID_STS_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20F0) /* EP1_LOCAL_CPL_ID_STS_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_ID_STS_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20F4) /* EP1_LOCAL_CPL_ID_STS_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_ID_STS_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20F8) /* EP1_LOCAL_CPL_ID_STS_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_ID_STS_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x20FC) /* EP1_LOCAL_CPL_ID_STS_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_ID_STS_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2100) /* EP0_REMOTE_CPL_ID_STS_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_ID_STS_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2104) /* EP0_REMOTE_CPL_ID_STS_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_ID_STS_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2108) /* EP0_REMOTE_CPL_ID_STS_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_ID_STS_3_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x210C) /* EP0_REMOTE_CPL_ID_STS_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_ID_STS_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2110) /* EP1_REMOTE_CPL_ID_STS_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_ID_STS_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2114) /* EP1_REMOTE_CPL_ID_STS_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_ID_STS_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2118) /* EP1_REMOTE_CPL_ID_STS_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_ID_STS_3_REG      (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x211C) /* EP1_REMOTE_CPL_ID_STS_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_ID_STS_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2120) /* EP0_REMOTE_P_ID_STS_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_ID_STS_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2124) /* EP0_REMOTE_P_ID_STS_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_ID_STS_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2128) /* EP0_REMOTE_P_ID_STS_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_ID_STS_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x212C) /* EP0_REMOTE_P_ID_STS_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_ID_STS_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2130) /* EP1_REMOTE_P_ID_STS_0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_ID_STS_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2134) /* EP1_REMOTE_P_ID_STS_1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_ID_STS_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2138) /* EP1_REMOTE_P_ID_STS_2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_ID_STS_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x213C) /* EP1_REMOTE_P_ID_STS_3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_LOCAL_TLP_P_ST_CFG_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2140) /* LOCAL_TLP_P_ST_CFG */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PREFIX_INF_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2144) /* EP0_ATOMIC_PREFIX_INF */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PREFIX_INF_REG        (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2148) /* EP1_ATOMIC_PREFIX_INF */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_ATOMIC_PF_VF_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x214C) /* ATOMIC_PF_VF */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_PORT_IDLE_STS_REG                (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2150) /* PORT_IDLE_STS */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_REMOTE_TLP_NUM_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2154) /* EP0_REMOTE_TLP_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_LOCAL_TLP_NUM_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2158) /* EP0_LOCAL_TLP_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_REMOTE_TLP_NUM_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x215C) /* EP1_REMOTE_TLP_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_LOCAL_TLP_NUM_REG            (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2160) /* EP1_LOCAL_TLP_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_SQCQ_TLP_NUM_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2164) /* SQCQ_TLP_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP0_CPL_NUM_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2168) /* EP0_CPL_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_EP1_CPL_NUM_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x216C) /* EP1_CPL_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_INF_BACK_PRESS_STS_REG           (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2170) /* INF_BACK_PRESS_STS */
#define HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_PORT_LINKDOWN_EVENT_REG          (HiPCIECTRL40V200_HIPCIEC_AP_DMA_REG_BASE + 0x2174) /* PORT_LINKDOWN_EVENT */

#endif // __HIPCIEC_AP_DMA_REG_REG_OFFSET_H__
